Research Progress on Materials and Devices of HgCdTe p-on-n Double Layer Heterojunction Grown by VLPE
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摘要: 本文对比分析了碲镉汞p-on-n器件四种制备方式的优劣，其中，VLPE（Vertical Liquid Phase Epitaxy）技术具有原位As掺杂与高激活率的技术优势，是制备高性能p-on-n双层异质结器件的重要方式。针对该技术，从材料生长、器件工艺和器件性能方面回顾了国内外研究进展，讨论了国内外差距，明确了制约该技术发展的关键问题和技术难点，并提出了解决思路。最后，展望了VLPE技术p-on-n异质结器件的发展趋势。
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关键词:
- 碲镉汞 /
- p-on-n /
- 台面异质结 /
- 富汞垂直液相外延(VLPE)
Abstract: This paper compares four different fabrication methods for mercury cadmium telluride (HgCdTe) p-on-n devices. Among these methods, vertical liquid-phase epitaxy (VLPE) stands out because of its unique advantages, particularly the high activation rate of in situ arsenic (As) dopants. VLPE is an essential approach for producing high-performance p-on-n double heterojunction devices. This paper reviews the research progress, both domestically and internationally, covering material growth, device processes, and performance. The discrepancies between domestic and foreign research are discussed, and the key challenges and technical bottlenecks hindering VLPE technology development are identified. Several solutions have been proposed to solve this problem. This study provides insights into the future trends of VLPE technology for p-on-n heterojunction devices, which hold significant promise in semiconductor devices.-
Keywords:
- HgCdTe /
- p-on-n /
- mesa heterojunction /
- VLPE
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图 4 Cd饱和度对VLPE MCT材料表面缺陷密度的影响：CdTe过饱和时，材料表面缺陷随机分布且缺陷密度较高，石墨舟上附着一层较厚的母液，(a)为CdTe过饱和时表面缺陷分布，(b)为CdTe过饱和时不同大小的表面缺陷的密度统计，(c) CdTe过饱和时石墨舟及碲镉汞薄膜表面形貌；优化CdTe饱和度后，材料表面缺陷密度下降，石墨舟上母液附着层变薄，(d)为CdTe饱和度优化后表面缺陷分布，(e)为CdTe饱和度优化后不同大小的表面缺陷的密度统计，(f) CdTe饱和度优化后石墨舟及碲镉汞薄膜表面形貌[24]
Figure 4. Influence of CdTe saturation on the surface defect density of VLPE MCT materials: When CdTe is oversaturated, surface defects exhibit a random distribution with a relatively high defect density. The graphite boat bears a thick layer of mother liquor. (a) Illustrates the distribution of surface defects during CdTe oversaturation. (b) Provides statistical data on the density of surface defects of varying sizes. (c) Depicts the surface morphology of the graphite boat and the HgCdTe film during CdTe oversaturation. After optimizing CdTe saturation, the material's surface defect density decreases, and the mother liquor layer on the graphite boat. becomes thinner. (d) Shows the surface defect distribution after optimizing CdTe saturation. (e) Presents statistics on the density of surface defects of different sizes.(f) Displays the surface morphology of the graphite boat and the CdTe film after saturation optimization.
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图 7 干法刻蚀与湿法腐蚀结合制备的台面隔离结构：先用低能量、大角度离子刻蚀光刻胶，再用湿化学法腐蚀MCT(a)，最后用高能量、小角度离子纵向刻蚀MCT(b)，形成高深宽比台面隔离槽(c)[48-49]
Figure 7. Mesa isolation structure prepared by combining dry etching and wet corrosion: first, low-energy, large-angle ion etching is used to remove photoresist, then MCT is corroded by wet chemical method (a), and finally, high-energy, small-angle ion longitudinal etching (b) and high depth-width ratio tabletop isolation trench (c) [48-49]
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图 8 p-on-n器件的台面刻蚀与侧壁钝化SEM形貌：台面焦平面阵列[45] (a)以及CdTe钝化层与HgCdTe的界面：(b)台面左侧CdTe/ HgCdTe界面；(c)台面右侧CdTe/ HgCdTe界面；(d)台面底部CdTe/ HgCdT界面[50]
Figure 8. SEM morphology of mesa etching and sidewall passivation of p-on-n devices: Mesa focal plane array (a) and left side interface of CdTe/ HgCdTe (b), right side interface of CdTe/ HgCdTe (c) and bottom side of CdTe/ HgCdTe (d)[50]
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图 9 Raytheon公司基于VLPE技术制备的p-on-n台面结器件在78 K工作温度下R0A与截止波长的关系(a)和量子效率(b)以及应用组件(c)[39-40]
Figure 9. Performance of p-on-n mesa devices based on VLPE technology: (a) relationship between R0A and cut-off wavelength at 78 K operating temperature, (b) quantum efficiency and (c) application components at Raytheon [39-40]
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图 12 pn结位置对暗电流和量子效率的影响：(a)为暗电流随pn结进入cap层的深度增加而增大，(b)为暗电流最优区；(c)为量子效率随pn结进入cap层的深度增加而降低，(d)为量子效率最优区[44, 57]
Figure 12. Influence of pn junction position on dark current and quantum efficiency: (a) Shows how dark current increases as the pn junction penetrates the cap layer, (b) represents the optimal region for dark current; (c) quantum efficiency decreases as the pn junction enters the cap layer, (d) depicts the optimal region for quantum efficiency. [44, 57]
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