Research on High-Speed Data Transmission Model of Large-Format High-Frame-Rate Readout Integrated Circuit
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摘要: 本文针对大规模高帧频读出电路的数字信号输出建立了高速数据传输模型。首先由集总参数模型得到传输电路3 dB带宽及响应时间常数与各器件参数之间的关系，指明了输出级MOS管的尺寸及传输线负载是决定高速时域响应特性的关键参数。进一步采用分布参数模型，利用Elmore延时模型更精确地确定了响应时间常数的数学解析式，获得了可使带宽最大化的输出级尺寸的最优设计。仿真结果表明，在典型的64×64面阵功耗和面积约束条件下，优化后传输门和复合逻辑门两种三态传输电路的输出3 dB带宽分别可达293 MHz和395 MHz。
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关键词:
- 大规模高帧频读出 /
- 数据传输模型 /
- Elmore延时模型
Abstract: In this paper, a high-speed data transmission model is presented for the digital signal output of a large-format high-frame-rate readout integrated circuit. We utilize the lumped parameter model to investigate the relationship between 3 dB bandwidth, response time, and device parameters. It is indicated that the size of the driver and the load of the transmission bus are the key parameters that determine the high-speed time-domain response characteristics. Furthermore, by using the distributed parameter model and Elmore delay model, the analytic expression for response time is deduced with more accurate values, and the optimal design of the output stage toward maximum bandwidth is obtained. Under the typical constraint condition of layout and power dissipation in a 64×64 array, simulation results show that the output 3 dB bandwidth of the transmission gate and composite logic gate can reach 293 MHz and 395 MHz, respectively. -
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图 1 读出电路及其传输电路结构（a：基于传输门的三态电路；b：基于复合逻辑门的三态电路）
Figure 1. Structure of transmission circuit: (a: Three-state circuit based on transmission gate; b: Three-state circuit based on composite logic gate)
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图 2 传输门结构驱动和输出级的集总等效电路
Figure 2. The lumped equivalent circuit of drive and output stage based on transmission gate
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图 3 响应时间常数与充放电电流的关系
Figure 3. Relationship between response time constant and charge-discharge current
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图 4 复合逻辑门结构驱动和输出级的集总等效电路
Figure 4. The lumped equivalent circuit of drive and output stages based on composite logic gate
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图 5 第i个像元输出的等效树形结构RC链
Figure 5. RC chain with equivalent tree structure for i-th pixel output stage
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图 6 输出带宽与传输线宽度的关系曲线
Figure 6. Relation curves between output bandwidth and transmission line width
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图 7 3 dB带宽与传输门尺寸的关系曲线
Figure 7. Relationship between 3 dB bandwidth and transmission gate size
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图 8 平均电流与传输门尺寸的关系曲线
Figure 8. Relationship between average current and transmission gate size
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图 9 传输线宽度对输出带宽（a）和平均电流（b）的影响
Figure 9. Influence of transmission line width on output bandwidth (a) and average current (b)
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[1] Richardson J, Walker R, Grant L, et al. A 32× 32 50ps resolution 10 bit time to digital converter array in 130 nm CMOS for time correlated imaging[C]//IEEE Custom Integrated Circuits Conference. IEEE, 2009: 77-80.
[2] Gersbach M, Maruyama Y, Trimananda R, et al. A time-resolved, low-noise single-photon image sensor fabricated in deep-submicron CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2012, 47(6): 1394-1407. http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=65A94AB0057DF293499DE4205CA62279?doi=10.1.1.418.1952&rep=rep1&type=pdf
[3] Field R M, Realov S, Shepard K L. A 100 fps, time-correlated single-photon-counting-based fluorescence-lifetime imager in 130 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2014, 49(4): 867-880. DOI: 10.1109/JSSC.2013.2293777
[4] YANG X, ZHU H, Nakura T, et al. A 15×15 single photon avalanche diode sensor featuring breakdown pixels extraction architecture for efficient data readout[J]. Japanese Journal of Applied Physics, 2016, 55(4S): 04EF04. DOI: 10.7567/JJAP.55.04EF04
[5] NIE K, WANG X, QIAO J, et al. A full parallel event driven readout technique for area array SPAD FLIM image sensors[J]. Sensors, 2016, 16(2): 160. DOI: 10.3390/s16020160
[6] Shawkat M S A, Mcfarlane N. A digital CMOS silicon photomultiplier using perimeter gated single photon avalanche diodes with asynchronous AER readout[J]. IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2020, 67(12): 4818-4828. DOI: 10.1109/TCSI.2020.2997358
[7] Buchholz J, Krieger J, Bruschini C, et al. Widefield high frame rate single-photon SPAD imagers for SPIM-FCS[J]. Biophysical Journal, 2018, 114(10): 2455-2464. DOI: 10.1016/j.bpj.2018.04.029
[8] Aull B F, Duerr E K, Frechette J P, et al. Large-format geiger-mode avalanche photodiode arrays and readout circuits[J]. IEEE Journal of Selected Topics in Quantum Electronics, 2017, 24(2): 1-10.
[9] Cominelli A, Acconcia G, Peronio P, et al. Readout architectures for high efficiency in time-correlated single photon counting experiments-analysis and review[J]. IEEE Photonics Journal, 2017, 9(3): 1-15.
[10] Rabaey J M, Chandrakasan A P, Nikolić B. Digital Integrated Circuits: A Design Perspective[M]. Upper Saddle River, NJ: Pearson education, 2003.
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