基于VLPE技术的碲镉汞p-on-n双层异质结材料与器件研究进展

王文金, 孔金丞, 起文斌, 张阳, 宋林伟, 吴军, 赵文, 俞见云, 覃钢

王文金, 孔金丞, 起文斌, 张阳, 宋林伟, 吴军, 赵文, 俞见云, 覃钢. 基于VLPE技术的碲镉汞p-on-n双层异质结材料与器件研究进展[J]. 红外技术, 2024, 46(3): 233-245.
引用本文: 王文金, 孔金丞, 起文斌, 张阳, 宋林伟, 吴军, 赵文, 俞见云, 覃钢. 基于VLPE技术的碲镉汞p-on-n双层异质结材料与器件研究进展[J]. 红外技术, 2024, 46(3): 233-245.
WANG Wenjin, KONG Jincheng, QI Wenbin, ZHANG Yang, SONG Linwei, WU Jun, ZHAO Wen, YU Jianyun, QIN Gang. Research Progress on Materials and Devices of HgCdTe p-on-n Double Layer Heterojunction Grown by VLPE[J]. Infrared Technology , 2024, 46(3): 233-245.
Citation: WANG Wenjin, KONG Jincheng, QI Wenbin, ZHANG Yang, SONG Linwei, WU Jun, ZHAO Wen, YU Jianyun, QIN Gang. Research Progress on Materials and Devices of HgCdTe p-on-n Double Layer Heterojunction Grown by VLPE[J]. Infrared Technology , 2024, 46(3): 233-245.

基于VLPE技术的碲镉汞p-on-n双层异质结材料与器件研究进展

基金项目: 

基础加强计划技术领域项目 2019-JCJQ-JJ527

详细信息
    作者简介:

    王文金(1997-),男,云南曲靖人,助理工程师,硕士研究生,研究方向是光电材料。E-mail: wangwenjin211@163.com

    通讯作者:

    孔金丞(1979-),男,云南南华人,研究员级高级工程师,博士生导师,主要从事光电材料与器件研究。E-mail: kongjincheng@163.com

  • 中图分类号: TN215

Research Progress on Materials and Devices of HgCdTe p-on-n Double Layer Heterojunction Grown by VLPE

  • 摘要: 本文对比分析了碲镉汞p-on-n器件四种制备方式的优劣,其中,VLPE(Vertical Liquid Phase Epitaxy)技术具有原位As掺杂与高激活率的技术优势,是制备高性能p-on-n双层异质结器件的重要方式。针对该技术,从材料生长、器件工艺和器件性能方面回顾了国内外研究进展,讨论了国内外差距,明确了制约该技术发展的关键问题和技术难点,并提出了解决思路。最后,展望了VLPE技术p-on-n异质结器件的发展趋势。
    Abstract: This paper compares four different fabrication methods for mercury cadmium telluride (HgCdTe) p-on-n devices. Among these methods, vertical liquid-phase epitaxy (VLPE) stands out because of its unique advantages, particularly the high activation rate of in situ arsenic (As) dopants. VLPE is an essential approach for producing high-performance p-on-n double heterojunction devices. This paper reviews the research progress, both domestically and internationally, covering material growth, device processes, and performance. The discrepancies between domestic and foreign research are discussed, and the key challenges and technical bottlenecks hindering VLPE technology development are identified. Several solutions have been proposed to solve this problem. This study provides insights into the future trends of VLPE technology for p-on-n heterojunction devices, which hold significant promise in semiconductor devices.
  • 电子倍增电荷耦合器件(Electron Multiply Charge Couple Device,EMCCD),是对传统CCD的功能升级,在信号电荷转移读出时,利用碰撞电离的物理机制,实现雪崩放大,从而越过读出噪声的门槛,降低等效读出噪声。这种方法解决了传统CCD在高速读出速率下,电荷检测放大器噪声降低至亚电子量级的技术难题,在1000倍增益下,等效读出噪声<1e,理论上可以达到单光子的探测灵敏度,实现了对微弱光的高帧率和高信噪比成像探测。

    2001年,TI公司的Hynecek[1]在虚相CCD工艺基础上增加了CCM(Charge Carrier Multiplier,电荷载流子倍增)结构,提出了栅分立虚相CCD(Split-Gate Virtual-Phase CCD,SGVPCCD)技术。同年,e2v公司Jerram[2]采用更为传统的CCD电极,提出了LLL CCD(Low-Light-Level CCD,低照度CCD)技术。这两条技术途径中,LLL CCD避免了SGVPCCD虚相电极倍增杂散电荷过多的问题,并且通过流水线的倍增形式,降低了倍增方差带来的非均匀性,成为EMCCD的主流技术,并发展了近20年。e2v公司从CCD65这第一款采用该技术的EMCCD开始,围绕前照、背照、减小噪声、减小时钟感生电荷、提高分辨率、提高读出速率等维度发展出了CCD97、CCD216、CCD201、CCD351(30 MHz读出速率)、CCD220(1300 fps)、CCD282(4 k×4 k)等多款器件。

    EMCCD超高的探测灵敏度,使其在成像科学仪器领域中获得应用,比如超分辨[3-5]、单分子[6-8]、离子成像[9]、共聚焦显微镜[10-11]、量子[12]、荧光成像[13-14]等。此外,在激光主动成像[15]、高灵敏度星敏感器[16]、微光夜视等领域中也有较多研究与应用。

    针对由华东光电集成器件研究所研制生产的一款640×512分辨率,帧转移结构的EMCCD器件,设计了一款相机。该款相机支持Camera Link和PAL视频输出、帧率25 fps、支持手动和自动电子倍增增益控制、TEC恒温控制、实时成像、尺寸55 mm×55 mm×70 mm。本文重点论述了相机工作时序和对应的代码,基于FPGA完成了对EMCCD的驱动、EMCCD输出信号的模数转换、PAL模拟视频编码和Camera Link数字视频编码的时序设计与实现,并完成了相关的成像测试工作。

    器件结构如图 1所示,包含有感光区、存储区、水平移位寄存器、增益寄存器和浮置扩散放大器(Floating Diffusion Amplifier,FDA)。其中,感光区有640×512个有效像素,上下各8个暗参考行,左右各12个暗列。存储区有664×528个存储单元,在感光区完成曝光后,存储转移下来的信号电荷。水平移位寄存器包含664组水平转移栅电极(RФ1、RФ2、RФ3),经过16组转角单元后进入664组增益寄存器(RФ1、RФDC、RФ2HV、RФ3),再经过16组过扫单元将信号电荷转移至浮置扩散区,将电荷转换成电压,最后经片上源跟随器电路放大读出。

    图  1  EMCCD器件结构
    Figure  1.  EMCCD device structure

    640×512 EMCCD相机的设计目标是能在1×10-3 lx照度下,实现25 fps的动态连续成像,输出8 bit的PAL模式视频流和12 bit的Camera Link数字视频流。相机硬件电子学的部分由驱动电路、信号处理电路和电源电路构成。本文重点介绍产生工作时序的信号处理电路部分,这部分由FPGA、SRAM、Flash、PAL编码芯片组成,产生了EMCCD的工作时序、ADC的采样时序、SRAM帧缓存时序、BT.656编码时序和Camera Link编码时序。

    EMCCD的工作时序如图 2所示。器件首先进行曝光,此时IФ1、IФ2、SФ1、SФ2拉低,感光区的像素单元(掩埋型MOS电容器)对光子进行积分,完成光电转换。在一定曝光时间后,IФ1、IФ2、SФ1、SФ2高低电平交替528个周期,将感光区的信号电荷转移至存储区。在信号电荷水平读出之前,用一定的时间(一般大于行读出时间的两倍)来清空水平转移栅极下势阱内的残余电荷。接着,SФ1、SФ2高低交替1次,构成一行读出的起始,将存储区的信号电荷转移至水平移位寄存器(MOS电容器)中。经过680个RФ1、RФ2、RФ2HV、RФ3转移周期后,一行中每个像素的信号电荷按顺序到达FD,此处的PN结二极管电容在接收信号电荷前,由ФR进行复位,再将信号电荷转成电压,由后级源跟随器读出。

    图  2  EMCCD工作时序
    Figure  2.  EMCCD work timing

    当前帧在水平读出时,感光区可以同时进行曝光,这种流水线操作的读出模式,使得成像延迟在1帧时间。

    这里为了实现25 fps的成像帧频,曝光时间是帧频的倒数即40 ms,根据靶面分辨率和其它动作的时间要求,设置水平读出的像素时钟频率为11 MHz。根据图 2,EMCCD的工作时序包含多个状态,分别是空闲(IDLE)、第一个10 μs脉冲(FIRST_PULSE)、垂直转移(FRAME_READOUT)、最后一个脉冲(LAST_PULSE)、水平读出寄存器清空(LINE_REG_CLEAN)、行读出(LINE_READOUT)和曝光控制(EXPOSURE_CTRL),通过使能信号和结束信号来控制状态间的跳转。

    EMCCD输出的模拟信号需通过AFE按顺序进行直流重建、相关双采样、增益控制、光学暗电平钳位和模数转换,以实现在数字域的处理和编码。涉及到的时序控制有相关双采样(SHP/SHD信号)、光学暗电平嵌位(CLPOB信号)、帧头行头的数据锁存。其中图 3中的SHP和SHD信号分别对复位信号和EMCCD输出信号进行采样,可以有效消除FD处复位带来的复位噪声(kTC噪声)[17]。此外,AFE为了能够在相对快速的同时获得高分辨率(10~13位),采用pipeline结构的ADC,图 3表明了当前采样值需要经过10个数据时钟后读出,所以在数据锁存时需要响应的延迟以保证像素数据的准确。

    图  3  SHP、SHD信号以及数字信号的流水线输出延迟
    Figure  3.  SHP、SHD signal and data bus pipeline delay

    光学暗电平钳位在每行光学暗像素的间隔内,ADC的输出与设定的暗电平参考进行比较,其结果经滤波后移除信号链上的残余偏移,追踪CCD暗电平中的低频变量。

    这段时序的代码与EMCCD的驱动时序同步,通过计数器与标志位标明帧同步、行同步和有效数据信号。

    模拟电视系统具有方便实时显示的优势,所以针对640×512分辨率,这里采用PAL制式作为模拟电视的输出,通过逐行变隔行和插值拉伸,输出720×576的模拟视频信号,方便调试与外场成像测试工作。

    根据ITU-R BT.656标准,一个完整的PAL视频帧分为两场(表 1),共625行,每行1728个27 MHz像素时钟。每行(表 2)则由4个部分组成,EAV码、水平消隐、SAV码和有效数据(4:2:2 YCbCr数据)。对于顶场,有效数据行就是一帧图像的所有偶数行,而底场,有效数据行就是一帧图像的所有奇数行。

    表  1  PAL视频帧的格式定义
    Table  1.  PAL frame definition
    Lines Line Description
    1~22 Field1-First Vertical Blanking(Top)
    23~310 Field1-Active Video
    311~312 Field1-Second Vertical Blanking(Bottom)
    313~335 Field2-First Vertical Blanking(Top)
    336~623 Field2-Active Video
    624~625 Field2-Second Vertical Blanking(Bottom)
    下载: 导出CSV 
    | 显示表格
    表  2  每行的数据结构
    Table  2.  Line data structure
    EAV code Blanking Video SAV code Active Video
    FF 0 0 EAV Cb Y Cr Y 255 0 0 SAV Cb Y Cr Y
    4 bytes 280 bytes 4 bytes 1440 bytes
    下载: 导出CSV 
    | 显示表格

    水平消隐包含280个字节,CbCr以0x80填充,Y以0x10填充。有效数据的顺序是CbYCrY,其中Y是亮度信号,CbCr是同地址的色差信号,YCbCr与RGB的转换公式如下:

    $$ Y=16+0.527R+0.504G+0.098B $$ (1)
    $$ C_{\rm{b}}=128-0.148R-0.291G+0.439B $$ (2)
    $$ C_{\rm{r}}=128+0.439R-0.367G-0.071B $$ (3)

    R(0~255),G(0~255),B(0~255)转换至Y(16~235),Cb(16~240),Cr(016~240)。由于EMCCD输出灰度图像,对应RGB值均相同,所以有效数据中Y的填充对应AFE输出的高8位数据,CbCr则为0x80。按照BT.656编码后的数字信号视频流经过ADV7391转换成模拟视频信号。

    640×512逐行扫描EMCCD的输出信号按BT.656编码,需要进行逐行到隔行的转换,并按照每8行插值1行,一行中每8个像素插值1个像素的插值方法对图像进行拉伸。通过一片片外的SRAM将一帧图像进行缓存。代码设计在27 MHz的时钟下,每经过一个像素时钟,像素计数(pixel_cnt)加1,计数满1727后清零,行计数(line_cnt)加1,计数满624后清零。按照ITU-R BT.656的数据要求,对每个像素进行赋值,当需要写入Y数据时,SRAM读地址(sram_rd_addr)相应加1,读取SRAM中对应的数据。由于仅有一片SRAM,所以需要对其地址总线和数据总线进行分时的读写操作,在不读SRAM的时候,AFE的数据通过FIFO根据SRAM写地址(sram_ wr_addr)写入SRAM。

    SRAM地址总线赋值如下,assign sram_addr = sram_rd_en? sram_rd_addr:sram_wr_addr。

    Camera Link是专门针对机器视觉应用领域的串行通信协议,使用LVDS(低压差分信号)进行数据的传输和通信[18]。这里为了实现对相机原始数据的采集,分析器件的性能,图像信噪比等参数,采用Camera Link作为数字视频信号的接口,经采集卡在上位机软件上进行图像显示。

    Camera Link协议的本质是Channel Link协议。主要包括5对差分信号线,其中4对为视频数据线,1对为同步的时钟信号。相机将28位并行数据信号按照7:1的比例将数据转换为4对差分对。Channel Link总线上除了传输视频数据外,还包括视频有效信号FVAL(帧有效)、LVAL(行有效)、DVAL(数据有效)。

    一个Channel Link只支持28位数据,所以对于更多的信号,需要多个并行的Channel Link来拓展带宽。据此Camera Link分为Base、Medium和Full三种配置,分别对应1路、2路和3路,每8位(一个Byte)作为一个端口,Full配置对应了A~H个端口。由于这里研制的相机输出12 bit的数字信号,所以只需要Base配置,对应port A[0:7]和port B[0:3]。LVAL、FVAL、DVAL、Spare,以及12 bit数字信号与Camera Link 28位数据的映射关系如表 3所示,其中没有用到的信号位拉低。

    表  3  Camera Link位分配
    Table  3.  Camera Link Bit Assignment
    Tx Input Signal Name Pin Name
    LVAL TX/RX 24
    FVAL TX/RX 25
    DVAL TX/RX 26
    Spare TX/RX 23
    Port A0 TX/RX 0
    Port A1 TX/RX 1
    Port A2 TX/RX 2
    Port A3 TX/RX 3
    Port A4 TX/RX 4
    Port A5 TX/RX 6
    Port A6 TX/RX 27
    Port A7 TX/RX 5
    Port B0 TX/RX 7
    Port B1 TX/RX 8
    Port B2 TX/RX 9
    Port B3 TX/RX 12
    下载: 导出CSV 
    | 显示表格

    在硬件设计上直接利用FPGA的IO口实现LVDS的输出。同时,通过补零将12 bit的数字信号凑齐至28位,并增加一路7 bit的数据1100011来模拟时钟信号。由于Camera Link采集卡上的接收芯片只支持20~85 MHz的数据信号,而AFE的数据信号同步在11 MHz的时钟上,所以需要一个异步FIFO完成数据的同步。

    datain3 < = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, data[7], data[6]};

    datain2 < = {dval, fval, lval, 1'b0, 1'b0, 1'b0, 1'b0};

    datain1 < = {1'b0, 1'b0, 1'b0, 1'b0, data[11:9]};

    datain0 < = {data[8], data[5:0]};

    clkin < = {1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1};

    待转换的28位数和7位时钟数据为txdata = {datain3, datain2, datain1, datain0, clkin},最后利用ALTLVDS_TX的IP核按照7:1对数据进行串行化构成Channel Link的输出格式。

    在实验室进行低照度条件下的实时成像,用色温2856 K的积分球光源模拟环境照度1×10-3 lx,采用USAF-1951目标靶,镜头25 mm/f1.4,EMCCD增益倍数1000倍,器件内部TEC制冷温度0℃。

    相机实物与成像效果如图 4所示,通过模拟监视器和Cameralink采集软件显示视频图像。图 4右图中模拟视频和数字视频同步显示,PAL输出720×576分辨率,25 fps的8 bit视频流。图 5中CameraLink输出640×512分辨率,25 fps的12 bit视频流,选定区域内的空域信噪比为21.8 dB。

    图  4  相机实物与模拟、数字视频输出
    Figure  4.  Camera analog and digital output video
    图  5  成像选定区域的信噪比
    Figure  5.  Selected region mean SD and SNR value

    本文介绍了支持PAL视频输出和Camera Link输出的640×512分辨率EMCCD相机的关键时序设计与实现,通过对EMCCD驱动,AFE数据同步采集,帧缓存PAL编码和Camera Link串并转换,实现了EMCCD器件在1×10-3 lx照度条件下的25 fps动态连续成像,实验证明该相机能同时输出PAL模拟视频和Camera Link数字视频,并且尺寸较小,低照度条件下信噪比优势突出,能满足微光条件下对目标成像的应用需求。

  • 图  1   MCT红外焦平面器件结构

    Figure  1.   Structure of MCT infrared focal plane device

    图  2   p-on-n器件制备方式

    Figure  2.   Fabrication process of p-on-n devices

    图  3   Raytheon公司p-on-n台面结器件结构(a)[39]和掺杂元素分布(b)[24]以及材料均匀性(c)[40]

    Figure  3.   Device Structure(a)[39] and doping profile(b)[24] and material uniformity(c)[40] of p-on-n mesa device at Raytheon

    图  4   Cd饱和度对VLPE MCT材料表面缺陷密度的影响:CdTe过饱和时,材料表面缺陷随机分布且缺陷密度较高,石墨舟上附着一层较厚的母液,(a)为CdTe过饱和时表面缺陷分布,(b)为CdTe过饱和时不同大小的表面缺陷的密度统计,(c) CdTe过饱和时石墨舟及碲镉汞薄膜表面形貌;优化CdTe饱和度后,材料表面缺陷密度下降,石墨舟上母液附着层变薄,(d)为CdTe饱和度优化后表面缺陷分布,(e)为CdTe饱和度优化后不同大小的表面缺陷的密度统计,(f) CdTe饱和度优化后石墨舟及碲镉汞薄膜表面形貌[24]

    Figure  4.   Influence of CdTe saturation on the surface defect density of VLPE MCT materials: When CdTe is oversaturated, surface defects exhibit a random distribution with a relatively high defect density. The graphite boat bears a thick layer of mother liquor. (a) Illustrates the distribution of surface defects during CdTe oversaturation. (b) Provides statistical data on the density of surface defects of varying sizes. (c) Depicts the surface morphology of the graphite boat and the HgCdTe film during CdTe oversaturation. After optimizing CdTe saturation, the material's surface defect density decreases, and the mother liquor layer on the graphite boat. becomes thinner. (d) Shows the surface defect distribution after optimizing CdTe saturation. (e) Presents statistics on the density of surface defects of different sizes.(f) Displays the surface morphology of the graphite boat and the CdTe film after saturation optimization.

    图  5   BAE公司p-on-n台面结器件结构(a)和掺杂浓度分布(b)[28]

    Figure  5.   Mesa device structure(a) and doping profile(b) of p-on-n at BAE [28]

    图  6   pn结界面C颗粒对p-on-n双层台面结器件性能的影响,C颗粒位置(a)与输出电压异常值(b)具有很好的对应关系[47]

    Figure  6.   Influence of C particles at pn junction interface on the performance of p-on-n dual-layer mesa devices, with a good correspondence between the position of C particles (a) and the abnormal output voltage (b) [47]

    图  7   干法刻蚀与湿法腐蚀结合制备的台面隔离结构:先用低能量、大角度离子刻蚀光刻胶,再用湿化学法腐蚀MCT(a),最后用高能量、小角度离子纵向刻蚀MCT(b),形成高深宽比台面隔离槽(c)[48-49]

    Figure  7.   Mesa isolation structure prepared by combining dry etching and wet corrosion: first, low-energy, large-angle ion etching is used to remove photoresist, then MCT is corroded by wet chemical method (a), and finally, high-energy, small-angle ion longitudinal etching (b) and high depth-width ratio tabletop isolation trench (c) [48-49]

    图  8   p-on-n器件的台面刻蚀与侧壁钝化SEM形貌:台面焦平面阵列[45] (a)以及CdTe钝化层与HgCdTe的界面:(b)台面左侧CdTe/ HgCdTe界面;(c)台面右侧CdTe/ HgCdTe界面;(d)台面底部CdTe/ HgCdT界面[50]

    Figure  8.   SEM morphology of mesa etching and sidewall passivation of p-on-n devices: Mesa focal plane array (a) and left side interface of CdTe/ HgCdTe (b), right side interface of CdTe/ HgCdTe (c) and bottom side of CdTe/ HgCdTe (d)[50]

    图  9   Raytheon公司基于VLPE技术制备的p-on-n台面结器件在78 K工作温度下R0A与截止波长的关系(a)和量子效率(b)以及应用组件(c)[39-40]

    Figure  9.   Performance of p-on-n mesa devices based on VLPE technology: (a) relationship between R0A and cut-off wavelength at 78 K operating temperature, (b) quantum efficiency and (c) application components at Raytheon [39-40]

    图  10   BAE公司基于LPE和VLPE技术制备的p-on-n台面结器件性能R0A(a)和量子效率(b) [51]

    Figure  10.   Performance of p-on-n mesa devices based on LPE and VLPE technology: R0A(a) and quantum efficiency (b) at BAE [51]

    图  11   碲镉汞探测器R0A值与77 K截止波长的关系[55]

    Figure  11.   MCT detector R0A product versus cutoff wavelength at 77 K, summarized with bibliographic data [55]

    图  12   pn结位置对暗电流和量子效率的影响:(a)为暗电流随pn结进入cap层的深度增加而增大,(b)为暗电流最优区;(c)为量子效率随pn结进入cap层的深度增加而降低,(d)为量子效率最优区[44, 57]

    Figure  12.   Influence of pn junction position on dark current and quantum efficiency: (a) Shows how dark current increases as the pn junction penetrates the cap layer, (b) represents the optimal region for dark current; (c) quantum efficiency decreases as the pn junction enters the cap layer, (d) depicts the optimal region for quantum efficiency. [44, 57]

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  • 收稿日期:  2023-07-13
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