一种提高FPGA片间通信稳定性的校验协议研究

池林辉; 钱芸生; 籍宇豪

一种提高FPGA片间通信稳定性的校验协议研究

南京理工大学，江苏南京 210094

基金项目:

省部级基金项目 61424120504162412001

详细信息

作者简介:
池林辉（1996-），男，硕士研究生，主要从事光电成像科研工作。E-mail：chilinhui6@163.com

通讯作者:
钱芸生（1968-），男，教授，博士生导师。主要从事光电测试、图像处理和仿真等工作。E-mail：yshqian@mail.njust.edu.cn

中图分类号: TN223
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- 文章访问数: 324
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- PDF下载量: 29
出版历程
- 收稿日期: 2020-07-02
- 修回日期: 2020-11-01
- 刊出日期: 2020-11-19

Verification Protocol for Improving Communication Stability Between FPGAs

Nanjing University of Science and Technology School of Electronic and Optical Engineering, Nanjing 210094, China

摘要

摘要: 随着FPGA（Field Programmable Gate Array）在大型系统中得到越来越广泛的应用，单片FPGA往往难以胜任全部工作，多片FPGA之间进行高速稳定通信成为了该领域的一个研究热点。为此设计了一种基于低压差分信号（low voltage differential signal，LVDS）可用于FPGA片间高速稳定通信的校验协议，该协议在常规LVDS通信的基础上进行多轮多路校验，以提高传输可靠性。基于该协议，搭建了一套由两片Xilinx 7系列FPGA构成的9通道LVDS通信测试系统。其中1个通道用于同步时钟，另外8通道用于校验和通信。经过长时间高低温测试，在保证单路传输速率达1.2 Gb/s的情况下，相对于常规LVDS通信，误码率大大降低。
- FPGA /
- LVDS /
- 通信测试 /
- 校验协议 /
- 高速稳定 /
- 误码率
Abstract: As field-programmable gate arrays(FPGAs) become increasingly used in large-scale systems, it is often difficult for a single-chip FPGA to perform all the tasks required. High-speed and stable communication between multiple FPGAs has become a focus of research in this field. For this purpose, a verification protocol based on low-voltage differential signaling (LVDS) that can be used for high-speed and stable communication between FPGA chips was designed. This protocol performs multiple rounds of multipath verification based on conventional LVDS communication to improve transmission reliability. Based on this protocol, a nine-channel LVDS communication test system consisting of two Xilinx 7 series FPGAs was built. One channel was used to synchronize the clock, and the other eight channels were used for checksum communication. After a long period of high- and low-temperature tests, the bit error rate was greatly reduced compared with conventional LVDS communications while ensuring a single transmission rate of 1.2 Gb/s.
- FPGA /
- LVDS /
- communication test /
- verification protocol /
- high speed and stability /
- bit error rate

HTML全文

图 1 片间通信测试系统组成框图

Figure 1. Block diagram of inter-chip communication test system

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图 2 硬件测试平台

Figure 2. Hardware test bench

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图 3 差分信号波形图

Figure 3. Differential signal waveform diagram

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图 4 通信原理框图

Figure 4. Communication schematic

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图 5 数据对齐流程图

Figure 5. Flowchart of data alignment

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图 6 信号在时间域抖动特性

Figure 6. Signal jitter characteristics in the time domain

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图 7 Bit位对齐时序图

Figure 7. Timing diagram of bit alignment

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图 8 Byte位对齐时序图

Figure 8. Timing diagram of Byte alignment

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图 9 双向校验示意图

Figure 9. Schematic diagram of two-way verification

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图 10 闭环校验示意图

Figure 10. Closed-loop verification diagram

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图 11 通信测试数据传输方案

Figure 11. Transmission plan of communication test data

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图 12 A7端ChipScope在线测试图

Figure 12. ChipScope online test chart of A7

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表 1 不同温度下FPGA片间通信误码率测试结果

Table 1 Test results of bit error rate of FPGA inter-chip communication at different temperatures

Temperature/℃ －30 －20 －10 0 10 20 30 40 50

Bit error rate 0 0 0 0 0 0 0 0 0

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