Abstract: The fast Fourier transform (FFT) is widely used in signal processing. However, traditional FFT processing usually needs to fill zeros when dealing with non-power-of-two points, which not only wastes considerable resources but also increases the processing time. This study improved the two-parallel radix-MDC FFT architecture and developed a reconfigurable radix-MDC FFT architecture that reduced the number of multipliers by 50%. This architecture reconfigured the same hardware resources into radix-2, radix-3, and radix-2² processing units, and 16 FFT operations with 1024 points could be achieved. The architecture was implemented in Verilog. Experimental results showed that the optimum performance was achieved when using 25-bit fixed-point quantization, with an average error of 10^-4, a maximum error of 10^-3, and a quantization signal-to-noise ratio of 92.19 dB. Compared with other designs found in the literature, the FFT architecture developed in this study had fewer multiplier resources, the greatest computational efficiency, and good application prospects.