Verification Protocol for Improving Communication Stability Between FPGAs

CHI Linhui; QIAN Yunsheng; JI Yuhao

Volume 42 Issue 11

Nov. 2020

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CHI Linhui, QIAN Yunsheng, JI Yuhao. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology , 2020, 42(11): 1022-1027.

Citation:

CHI Linhui, QIAN Yunsheng, JI Yuhao. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology , 2020, 42(11): 1022-1027.

CHI Linhui, QIAN Yunsheng, JI Yuhao. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology , 2020, 42(11): 1022-1027.

Citation:

CHI Linhui, QIAN Yunsheng, JI Yuhao. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology , 2020, 42(11): 1022-1027.

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Verification Protocol for Improving Communication Stability Between FPGAs

Nanjing University of Science and Technology School of Electronic and Optical Engineering, Nanjing 210094, China

Received Date: 2020-07-03
Rev Recd Date: 2020-11-02
Publish Date: 2020-11-20

Abstract

Abstract

As field-programmable gate arrays(FPGAs) become increasingly used in large-scale systems, it is often difficult for a single-chip FPGA to perform all the tasks required. High-speed and stable communication between multiple FPGAs has become a focus of research in this field. For this purpose, a verification protocol based on low-voltage differential signaling (LVDS) that can be used for high-speed and stable communication between FPGA chips was designed. This protocol performs multiple rounds of multipath verification based on conventional LVDS communication to improve transmission reliability. Based on this protocol, a nine-channel LVDS communication test system consisting of two Xilinx 7 series FPGAs was built. One channel was used to synchronize the clock, and the other eight channels were used for checksum communication. After a long period of high- and low-temperature tests, the bit error rate was greatly reduced compared with conventional LVDS communications while ensuring a single transmission rate of 1.2 Gb/s.
- FPGA,
- LVDS,
- communication test,
- verification protocol,
- high speed and stability,
- bit error rate

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References(14)

References

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