Verification Protocol for Improving Communication Stability Between FPGAs
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摘要: 随着FPGA（Field Programmable Gate Array）在大型系统中得到越来越广泛的应用，单片FPGA往往难以胜任全部工作，多片FPGA之间进行高速稳定通信成为了该领域的一个研究热点。为此设计了一种基于低压差分信号（low voltage differential signal，LVDS）可用于FPGA片间高速稳定通信的校验协议，该协议在常规LVDS通信的基础上进行多轮多路校验，以提高传输可靠性。基于该协议，搭建了一套由两片Xilinx 7系列FPGA构成的9通道LVDS通信测试系统。其中1个通道用于同步时钟，另外8通道用于校验和通信。经过长时间高低温测试，在保证单路传输速率达1.2 Gb/s的情况下，相对于常规LVDS通信，误码率大大降低。Abstract: As field-programmable gate arrays(FPGAs) become increasingly used in large-scale systems, it is often difficult for a single-chip FPGA to perform all the tasks required. High-speed and stable communication between multiple FPGAs has become a focus of research in this field. For this purpose, a verification protocol based on low-voltage differential signaling (LVDS) that can be used for high-speed and stable communication between FPGA chips was designed. This protocol performs multiple rounds of multipath verification based on conventional LVDS communication to improve transmission reliability. Based on this protocol, a nine-channel LVDS communication test system consisting of two Xilinx 7 series FPGAs was built. One channel was used to synchronize the clock, and the other eight channels were used for checksum communication. After a long period of high- and low-temperature tests, the bit error rate was greatly reduced compared with conventional LVDS communications while ensuring a single transmission rate of 1.2 Gb/s.
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Key words:
- FPGA /
- LVDS /
- communication test /
- verification protocol /
- high speed and stability /
- bit error rate
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表 1 不同温度下FPGA片间通信误码率测试结果
Table 1. Test results of bit error rate of FPGA inter-chip communication at different temperatures
Temperature/℃ －30 －20 －10 0 10 20 30 40 50 Bit error rate 0 0 0 0 0 0 0 0 0 
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