微光探测成像系统电路设计与实现

姜婷; 陈伟男; 夏振涛; 胡继宝; 姜守望; 孙永雪; 李太平; 谢永权

微光探测成像系统电路设计与实现

上海卫星装备研究所, 上海 200240

详细信息

作者简介:
姜婷（1989-），女，江西上饶人，硕士，主要从事光电成像系统电子学技术方面的研究。E-mail：jiangting_sitp@163.com

中图分类号: TN215
计量
- 文章访问数: 120
- HTML全文浏览量: 60
- PDF下载量: 58
- 被引次数: 0
出版历程
- 收稿日期: 2021-03-10
- 修回日期: 2021-04-01
- 刊出日期: 2022-10-20

Design and Development of a Low-Light Detection Imaging System Circuit

Shanghai Institute of Spaceflight Equipment, Shanghai 200240, China

摘要

摘要: 为满足微光遥感卫星领域对微光探测的需求，本文提出了一种基于微光CMOS图像传感器GSENSE2020的成像电路设计。该成像电路通过FPGA实现了对图像传感器的驱动控制以及高速图像数据的接收和传输，通过DC/DC和LDO（low dropout regulator）为图像传感器提供了低噪声供电电源，采用PMIC（power management IC）解决了FPGA上电时序问题，利用DDR3实现高速图像缓存与处理，采用eMMC达到图像数据存储速率与容量的需求，应用FPGA的IP核及原语代替CameraLink接口转换芯片实现CameraLink通信协议，从而完成图像数据直接在CameraLink接口的高速传输。实验结果表明，成像系统电路功能及性能都达到了预期设计目标，系统的输出数据率可达2.4 Gbps，帧频高达25 fps，信噪比达到45.5 dB。
- 微光探测 /
- CMOS图像传感器 /
- FPGA /
- LDO /
- PMIC /
- DDR3 /
- eMMC /
- CameraLink
Abstract: To achieve low-light detection in low-light remote sensing satellites, an imaging circuit is designed based on a low-light complementary metal oxide semiconductor image sensor named GSENSE2020. The imaging circuit facilitates the drive control of the image sensor and the reception and transmission of high-speed image data through a field programmable gate array (FPGA), provides low-noise power supply for the image sensor through DC/DC and low-dropout regulator, and uses a power management integrated circuit to solve the problem of FPGA power-on timing. The circuit also uses DDR3 to perform high-speed image caching and processing and adopts an embedded multimedia card to meet the requirements of image data storage rate and capacity. The intellectual property core and primitives of the FPGA are used instead of a CameraLink interface conversion chip to establish the CameraLink communication protocol. Thus, the circuit can directly transmit image data with high speed to the CarameLink interface. The experimental results show that the circuit's functions and the performance of the imaging system reach the expected design goals. The output data rate of the system reaches 2.4 Gbps, frame rate reaches 25 fps, and signal-to-noise ratio reaches 45.5 dB.
- low-light detection /
- COMS image sensor /
- FPGA /
- LDO /
- PMIC /
- DDR3 /
- eMMC /
- CameraLink

HTML全文

图 1 成像系统电路结构

Figure 1. Imaging system circuit structure

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图 2 TPS7A8300设计电路

Figure 2. TPS7A8300 design circuit

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图 3 PMIC局部设计电路

Figure 3. PMIC partial design circuit diagram

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图 4 MT41K64M16TW设计电路

Figure 4. MT41K64M16TW design circuit

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图 5 KLMCG4JENB-B041设计电路

Figure 5. KLMCG4JENB-B041 design circuit

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图 6 FPFA的7:1并串转换

Figure 6. FPGA 7:1 parallel-serial converter module

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图 7 系统硬件电路实物

Figure 7. System hardware circuit physical diagram

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图 8 上电时序图

Figure 8. Power-on sequence diagram

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图 9 电源纹波

Figure 9. Power ripple

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图 10 图像帧频

Figure 10. Image frame rate display

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图 11 实景成像

Figure 11. Real scene imaging

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表 1 Base模式的端口分配

Table 1. Base mode port allocation

Input signal name	28-bit pin name	Input signal name	28-bit pin name
Strobe	TxClk Out/RxClk In	Port B2	TX/RX 9
LVAL	TX/RX 24	Port B3	TX/RX12
FVAL	TX/RX 25	Port B4	TX/RX 13
DVAL	TX/RX 26	Port B5	TX/RX 14
Spare	TX/RX 23	Port B6	TX/RX 10
Port A0	TX/RX 0	Port B7	TX/RX 11
Port A1	TX/RX 1	Port C0	TX/RX 15
Port A2	TX/RX 2	PortC1	TX/RX 18
Port A3	TX/RX 3	Port C2	TX/RX 19
Port A4	TX/RX 4	Port C3	TX/RX 20
Port A5	TX/RX 6	Port C4	TX/RX 21
Port A6	TX/RX 27	Port C5	TX/RX 22
Port A7	TX/RX 5	Port C6	TX/RX 16
Port B0	TX/RX 7	Port C7	TX/RX 17
Port B1	TX/RX 8	-	-

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