Research Progress of Dislocation Density Reduction in MBE HgCdTe on Alternative Substrates
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摘要: 分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。Abstract: HgCdTe has dominated the high-performance IR detector market for decades. Owing to its numerous merits, including precise energy band structure control and device structure growth, the MBE(molecular beam epitaxy) growth of HgCdTe has become the main tool for fabricating third-generation IR focal plane arrays. CdZnTe is widely considered to be an ideal substrate for HgCdTe epitaxy because of the matched lattice through Zn fraction adjustment. Therefore, HgCdTe/CdZnTe has a high crystal quality with a typical etch pit density in the range of 1×104–1×105 cm-2. However, several limitations, such as high cost, small wafer size, and low yield, still exist in the (211) CdZnTe substrate, which results in high cost and limits the array format size in infrared detectors based on HgCdTe/CdZnTe. Compared with CdZnTe substrates, alternative substrates (e.g., Si, Ge, GaAs, and GaSb) have large wafer size, low cost, and convenience in standard semiconductor equipment, which have the potential to fabricate low-cost high-performance focal plane arrays. The main issue in HgCdTe on alternative substrates is the large lattice mismatch between the substrate and epi-layer (19.3%, 14.3%, 14.4%, and 6.1% for Si, Ge, GaAs, and GaSb, respectively), which is responsible for the high dislocation density of 106–107 cm-2 in HgCdTe films. The high dislocation density hampers the application of this material to long-wavelength and very long-wavelength infrared detectors.The variation in dislocation density with film thickness in the as-grown HgCdTe film grown on an alternative substrate was modeled, and the results from the ρ~1/h law agreed well with the experimental data. This indicates that the dislocation annihilation radius is the leading cause of impeding the dislocation density below 5×106 cm-2 in HgCdTe; thus, dislocation reduction is urgently needed. Moreover, the theory and research progress on three dislocation reduction methods, namely thermal cycle annealing (TCA), dislocation blocking, and mesa dislocation gettering (MDG), are summarized in this paper. Prospects and priorities for future development are also discussed. Overall, TCA and dislocation blocking techniques are likely to be harder in technical breakthroughs and have less development potential in dislocation reduction to below 5× 105 cm-2. By contrast, the MDG technique has shown tremendous development potential and high value in low-cost long-wavelength infrared detectors; however, process integration between the MDG technique and standard focal plane array fabrication is needed.
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图 1 异质衬底上碲化镉、碲镉汞材料贯穿位错密度随厚度的变化规律
注:图内示意图为膜层结构及各特征位置位错密度标记,方形及圆形数据点来自文献[10]和文献[11],分别为Ge基碲化镉和Si基碲镉汞EPD数据,菱形点为昆明物理研究所(KIP)Ge基碲镉汞EPD数据
Figure 1. Threading dislocations density verse epi-layer thickness on alternative substrate
Note: The schematic of HgCdTe layer structure and dislocations density symbols at each typical position were showed at top of the figure
图 4 退火温度与位错抑制效果关系,点为实验结果,线为理论计算结果(每周期5 min):(a) 高温温度为604℃;(b) 高温温度为494℃;(c) 高温温度为440℃[16]
Figure 4. Relationship between ex-situ annealing temperature and EPD, The dots and line represent experimental and theoretical data(Each cycle holds 5 mins at annealing temperature): (a)T=604℃; (b)T=494℃; (c)T=440℃[16]
图 7 位错阻挡层结构及位错阻挡效果:(a) GaAs/Si界面附近In0.18Ga0.82As/GaAs阻挡层TEM照片;(b) GaAs/Si界面附近经多次位错过滤后位错密度的变化,位错阻挡层将位错密度降至1×106cm-2以下[25];(c) CdTe/GaSb界面处的Cd0.85Zn0.15Te/CdTe位错阻挡层结构示意图;(d) CdTe/GaSb材料阻挡层位错抑制效果,原生碲化镉EPD(上)及位错抑制后碲化镉EPD(下)[27]
Figure 7. Image of dislocation filtering layer structure and dislocation density change through filtering: (a) TEM image of In0.18Ga0.82As/GaAs blocking layer at the GaAs/Si interface; (b) Dislocation density at each position showed in (a)[25]; (c) Schematic of Cd0.85Zn0.15Te/CdTe blocking layer at CdTe/GaSb interface; (d) EPD comparison of CdTe on GaSb with and without dislocation filtering layers[27]
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