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异质衬底外延碲镉汞薄膜位错抑制技术进展

杨晋 李艳辉 杨春章 覃钢 李俊斌 雷文 孔金丞 赵俊 姬荣斌

杨晋, 李艳辉, 杨春章, 覃钢, 李俊斌, 雷文, 孔金丞, 赵俊, 姬荣斌. 异质衬底外延碲镉汞薄膜位错抑制技术进展[J]. 红外技术, 2022, 44(8): 828-836.
引用本文: 杨晋, 李艳辉, 杨春章, 覃钢, 李俊斌, 雷文, 孔金丞, 赵俊, 姬荣斌. 异质衬底外延碲镉汞薄膜位错抑制技术进展[J]. 红外技术, 2022, 44(8): 828-836.
YANG Jin, LI Yanhui, YANG Chunzhang, QIN Gang, LI Junbin, LEI Wen, KONG Jincheng, ZHAO Jun, JI Rongbin. Research Progress of Dislocation Density Reduction in MBE HgCdTe on Alternative Substrates[J]. Infrared Technology , 2022, 44(8): 828-836.
Citation: YANG Jin, LI Yanhui, YANG Chunzhang, QIN Gang, LI Junbin, LEI Wen, KONG Jincheng, ZHAO Jun, JI Rongbin. Research Progress of Dislocation Density Reduction in MBE HgCdTe on Alternative Substrates[J]. Infrared Technology , 2022, 44(8): 828-836.

异质衬底外延碲镉汞薄膜位错抑制技术进展

基金项目: 核高基重大专项项目
详细信息
    作者简介:

    杨晋(1990-),男,博士研究生,主要从事红外光电材料的研究工作。E-mail:buaamseyj@163.com

  • 中图分类号: TN304

Research Progress of Dislocation Density Reduction in MBE HgCdTe on Alternative Substrates

  • 摘要: 分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。
  • 图  1  异质衬底上碲化镉、碲镉汞材料贯穿位错密度随厚度的变化规律

    注:图内示意图为膜层结构及各特征位置位错密度标记,方形及圆形数据点来自文献[10]和文献[11],分别为Ge基碲化镉和Si基碲镉汞EPD数据,菱形点为昆明物理研究所(KIP)Ge基碲镉汞EPD数据

    Figure  1.  Threading dislocations density verse epi-layer thickness on alternative substrate

    Note: The schematic of HgCdTe layer structure and dislocations density symbols at each typical position were showed at top of the figure

    图  2  循环退火典型温度控制曲线[13]

    Figure  2.  Typical annealing temperature profile in thermal cycle annealing[13]

    图  3  两种位错反应类型示意[17]

    Figure  3.  Schematic of two types of dislocation reaction[17]

    图  4  退火温度与位错抑制效果关系,点为实验结果,线为理论计算结果(每周期5 min):(a) 高温温度为604℃;(b) 高温温度为494℃;(c) 高温温度为440℃[16]

    Figure  4.  Relationship between ex-situ annealing temperature and EPD, The dots and line represent experimental and theoretical data(Each cycle holds 5 mins at annealing temperature): (a)T=604℃; (b)T=494℃; (c)T=440℃[16]

    图  5  循环退火处理后碲镉汞薄膜理论最低位错密度与退火温度的关系,材料位错密度降低至5×105cm-2时所需的循环次数及时间与退火温度的关系

    Figure  5.  Relationship between theoretical lowest dislocation density and annealing temperature, and annealing cycles needed verse temperature when dislocation density below 5×105cm-2

    图  6  异质外延中贯穿位错进入外延层时发生偏转及沿界面延伸示意[22]:(a) 位错在界面处的偏转发生在滑移面内;(b) 位错在界面处发生偏转的截面示意

    Figure  6.  Schematic of threading dislocation bending and progressing along the interface of substrate and epi-layer[22]: (a) Threading dislocation bending within slip plane; (b) Section diagram

    图  7  位错阻挡层结构及位错阻挡效果:(a) GaAs/Si界面附近In0.18Ga0.82As/GaAs阻挡层TEM照片;(b) GaAs/Si界面附近经多次位错过滤后位错密度的变化,位错阻挡层将位错密度降至1×106cm-2以下[25];(c) CdTe/GaSb界面处的Cd0.85Zn0.15Te/CdTe位错阻挡层结构示意图;(d) CdTe/GaSb材料阻挡层位错抑制效果,原生碲化镉EPD(上)及位错抑制后碲化镉EPD(下)[27]

    Figure  7.  Image of dislocation filtering layer structure and dislocation density change through filtering: (a) TEM image of In0.18Ga0.82As/GaAs blocking layer at the GaAs/Si interface; (b) Dislocation density at each position showed in (a)[25]; (c) Schematic of Cd0.85Zn0.15Te/CdTe blocking layer at CdTe/GaSb interface; (d) EPD comparison of CdTe on GaSb with and without dislocation filtering layers[27]

    图  8  台面位错吸除处理的Si基碲镉汞制备的长波器件R0A值与碲锌镉基碲镉汞制备的长波器件R0A值比较[31]:(a) CZT衬底上生长的碲镉汞;(b) Si基碲镉汞

    Figure  8.  R0A comparison between LWIR FPAs made from HgCdTe/Si through mesa dislocation gettering and HgCdTe/CdZnTe[31]: (a) device fabricated by MCT on CZT and (b) on CdTe/Si

    图  9  不同方向长条台面位错抑制效果对比[34, 36]:(a) 沿不同晶向台面退火处理后EPD情况;(b) 不同晶向台面在不同退火条件处理后EPD情况

    Figure  9.  EPD comparison of long mesa structures with different orientation[34, 36]: (a) Micrograph after etching and (b) EPD value

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出版历程
  • 收稿日期:  2021-03-10
  • 修回日期:  2021-04-16
  • 刊出日期:  2022-08-20

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